With the advancement of fabrication technology, the resolution of active matrix electroluminescent displays (AMEL displays) and active matrix liquid crystal displays (AMLCD's) steadily has increased. However, use of such displays is limited by the rate at which video data can be transmitted from a video data source to the display. For example, with video entering a graphics memory at 30 frames per second (fps) to 60 fps, to maintain a desired state of a display, each pixel of the display must be electrically refreshed at least 30 to 60 times a second. The greater the resolution of a display, the greater the number of rows and columns of pixels that must be refreshed at a time, for example, at resolutions of 1280.times.1024 pixels, 30 fps to 60 fps would require 40-80 million pixels per second into and out of the graphics memory. Therefore, a need exists for a display architecture capable of transmitting the video data to the displays at high resolution display rates.
In addition, with a multitude of displays and display pixel formats available, numerous memory architecture designs are required to transmit video data between the video source and display for a multitude of display formats. With particular memory architectures designed for use with particular types of displays and display formats, such architectures are not interchangeable for use with a multitude of display formats. In many circumstances it would be beneficial to be able to utilize a memory architecture for two or more display formats. Thus, a need for such a memory architecture is apparent.